Our paper 'Algebraic Fault Analysis of SHA-3 under Relaxed Fault Models' has been accepted for publication in IEEE Transactions on Information Forensics and Security.

Our paper 'Differential Fault Analysis of SHA-3 under Relaxed Fault Models' has been accepted for publication in Journal of Hardware and Systems Security, Springer.

Chao presented our work, "Side-channel power analysis of XTS-AES", at DATE 2017 in Lausanne Switzerland.

The simulation code for the differential fault analysis of SHA-3 has been released for downloading.

The paper, "Algebraic fault analysis of SHA-3", has been accepted as long paper for Design Automation and Test in Europe (DATE) 2017. Congratulations, Pei.

The paper, "Side-channel power analysis of XTS-AES", has been accepted as long paper for Design Automation and Test in Europe (DATE) 2017. Congratulations, Chao.

Our paper, "Differential Fault Analysis of SHA3-224 and SHA3-256", is accepted for publication in FDTC 2016 - Thirteenth Workshop on Fault Diagnosis and Tolerance in Cryptography.

Our paper, "Concurrent Error Detection for Reliable SHA-3 Design", is accepted for publication in GLSVLSI'2016 - 26th ACM international conference on Great lakes symposium on VLSI.

Our paper, "A Complete Key Recovery Timing Attack on a GPU", is accepted for publication in HPCA 2016 (The 22nd International IEEE Symposium on High-Performance Computer Architecture).

Our paper, "A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks" is accepted for publication in Asiacrypt 2015 (21st Annual International Conference on the Theory and Application of Cryptology and Information Security). Congratulations, Liwei!

Our paper, "Leakage Evaluation on Power Balance Countermeasure Against Side-Channel Attack on FPGAs" is accepted for publication in 2015 IEEE High Performance Extreme Computing Conference (HPEC ‘15). . Congratulations, Xin!

Our paper, "Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks" and "Balance Power Leakage to Fight Against Side-Channel Analysis at Gate Level in FPGAs" are accepted for publication in ASAP 2015 - 26th IEEE International Conference on Application-specific Systems, Architectures and Processors.

Our paper, "Side-Channel Analysis of MAC-Keccak Hardware Implementations" is accepted for publication in 2015 Hardware and Architectural Support for Security and Privacy (HASP).

Our paper, "Efficient 2nd-order Power Analysis on Masked Devices Utilizing Multiple Leakage", is accepted for publication in Proc. Int. Symp. on Hardware Oriented Security and Trust (HOS'15T) . Congratulations, Liwei!

Congradulations to Neel Shah, Tushar Swamy, and Harrison Dimmig for winning the Best Cyber Security Solution for 2014 for their poster titled “Scalable Open-source Side-channel Evaluation Platform for Cryptographic Devices” at the Advanced Cyber Security Center Annual Conference. http://www.ece.neu.edu/news/poster-winners-acsc-conference

Two papers, "Power analysis attack on hardware implementation of MAC-Keccak on FPGAs" and "Side-channel power leakage analysis of different protection schemes on AES", have been accepted for publication in Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig'14). Congratulations, Pei!

A new Ph.D student, Chao Luo, has joined our project. Welcome onboard, Chao!

A new Ph.D student, Zhen Hang Jiang, has joined our project. Welcome onboard, Zhen!

We have received an REU(Research Experience for Undergraduates) supplement award of $24,000 from NSF for the MRI project: Development of a Testbed for Side Channel Analysis and Security Evaluation (TeSCASE).

Neel and Tushar have presented their work “Scalable and Efficient Implementation of Correlation Power Analysis Using Graphics Processing Units (GPUs)” in the 2014 Workshop on Hardware and Architectural Support for Security and Privacy (HASP), collocated with International Symposium on Computer Architecture (ISCA).

We have received an REU supplement award of $16,000 from NSF for the SaTC project: TWC: Medium: A Unified Statistics-based Framework for Side-channel Attack Analysis and Security Evaluation of Cryptosystems.