We implement the unmasked AES on Sasebo-GII board [1] and the source code are provided together with the board by RCIS [2]. We provide only $100,000$ traces for downloading because the unmasked AES is easy to attack and results show that only $5,000$ traces is enough to conquer the AES system with a success rate $100\%$. The $100,000$ traces are included in two packages ( 001_unmasked_AES.tbz2 002_unmasked_AES.tbz2) and each contains $50,000$ traces.

One example of power trace is shown in Fig. 1. There are 11 peaks in the power trace. The first peak is the loading of plaintext into the register and the following 10 peaks are 10 rounds of the AES. Details of the implementation can be found in [2]. Knowledge of Verilog is required to understand the implementation.

We attacked on the traces to recover the 16th byte of the last round key and the success rate is as in Fig. 1.

We also use these traces in our paper [3], [4] please refer these papers for details of correlations and success rate results of attacks.

[1] “Evaluation environment for side-channel attacks,” http://www.risec.aist.go.jp/project/sasebo/.

[2] “Side-channel attack standard evaluation board (sasebo): Sasebo-gii,” http://www.rcis.aist.go.jp/special/SASEBO/SASEBOGII-en.html.

[3] T. Swamy, N. Shah, P. Luo, Y. Fei, and D. Kaeli, “Scalable and efficient implementation of correlation power analysis using graphics processing units (gpus),” in Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy. ACM, 2014, p. 10.

[4] P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Side-channel power analysis of different protection schemes against fault attacks on AES,” in IEEE Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), 2014.